DFM&Y 2006 - Call for Papers

CALL FOR PAPERS

Scope -- Author Information -- Committees

Scope

Increased manufacturing susceptibility in today’s nanometer technologies requires up to date solutions for yield optimization. In fact, designing a SoC for manufacturability and yield aims at improving the manufacturing process and consequently its yield by enhancing communications across the design-manufacturing interface. A wide range of Design-for-Manufacturability (DFM) and Design-for-Yield (DFY) methodologies and tools are proposed today. Some of these are leveraged during the back-end design stages, and others have post-design utilization, from lithography up to wafer sort, packaging, final test and failure analysis. DFM and DFY can dramatically impact the business performance of chip manufacturers. It can also significantly affect age-old chip design flows. Using DFM and DFY solutions is an investment, and thus choosing the most cost effective one(s) requires trade-off analysis. The workshop analyzes this key trend and its challenges, and provides an opportunity to discuss a range of DFM and DFY solutions for today’s SoC designs.

Representative topics include, but are not limited to:

Analog and mixed-signal DFM
Built-in Repair Analysis and Self-Repair
Critical area analysis
DFM via adaptive design
Embedded Test and Diagnosis
Infrastructure IP
Optical proximity Correction
Process Monitoring IP
Reticle Enhancement Techniques
Statistical Design
Test-based Yield Learning
Variability-aware Design
Yield Enhancement IP
Yield Management

Author Information

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To present at the Workshop, authors are invited to submit paper proposals. The proposals may be extended abstracts (500 words) or full papers. Each submission should include: title, full name and affiliation of all authors, a short abstract of 50 words, and keywords. Also, identify a contact author and include a complete correspondence address, phone number, fax number, and e-mail address.

Submit a copy of your paper proposal by Postscript, or PDF, via E-mail. Proposals for panel discussions are also invited. Submissions are due no later than September 14, 2006.

Submit your paper proposal to:

Andrew B. Kahng, Blaze DFM, abk@blaze-dfm.com, Tel: +1-408-505-2396

Authors will be notified of the disposition of their papers by September 27, 2006.

Authors of accepted papers may submit an illustrated text by October 11, 2006 for inclusion in the Digest of Papers, which will be provided to the attendees.

Special Issue: The best contributions of DFM&Y 2006 will appear in a Special Issue of JETTA (the Journal of Electronic Testing: Theory and Applications).

For general information contact:

Yervant Zorian
Virage Logic Corp
Tel: +1-510-360-8035
Fax: +1-510-360-8078
E-mail: yzorian@computer.org

Committees

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General Chair
Yervant Zorian, Virage Logic

Co-General Chair
Juan-Antonio Carballo, IBM

Program Chair
Andrew B. Kahng, Blaze DFM

Publication
A. Ivanov, Univ British Columbia

Panels
R. Camposano, Synopsys

Finance
R. Aitken, ARM

Publicity
D. Gizopoulos, Univ Piraeus

Program Committee to include

D. Appello, STMicroelectronics
C. Bittlestone, Texas Instruments
A. Gattiker, IBM
K.S. Kim, Intel
F. Kurdahi, UC Irvine
H. Lee, Magma
A. Markosian, Ponte Solutions
D. Maynard, IBM
C. Metra, Univ of Bologna
M. Murakata, STARC
S. Nassif, IBM
M. Nicolaidis,TIMA
M. Orshansky, Univ of Texas
V. Pitchumani, Intel
J.M. Portal, Univ of Marseille
P. Prinetto, Pol. di Torino
R. Radojcic, Qualcomm
J. Rey, Mentor Graphics
A. Singh, Auburn Univ
D. Sylvester, Univ of Michigan
V. Vardanian, Virage Logic
B. Vermeulen, Philips
D.M.H. Walker, Texas A&M Univ
S. Wigley, LTX
C-W. Wu, National Tsing Hua Univ
H-J. Wunderlich, Univ of Stuttgart
G. Yeric, Synopsys

For more information, visit us on the web at: http://www.unipi.gr/dfmy

The 1st IEEE International Workshop on Design for Manufacturability & Yield (DFM&Y 2006) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC) and the IEEE Council on Electronic Design Automation (CEDA).